Optical pulsations from a transitional millisecond pulsar

Weakly magnetic, millisecond spinning neutron stars attain their very fast rotation through a 1E8-1E9 yr long phase during which they undergo disk-accretion of matter from a low mass companion star. They can be detected as accretion-powered millisecond X-ray pulsars if towards the end of this phase their magnetic field is still strong enough to channel the accreting matter towards the magnetic poles. When mass transfer is much reduced or ceases altogether, pulsed emission generated by particle acceleration in the magnetosphere and powered by the rotation of the neutron star is observed, preferentially in the radio and gamma-ray bands. A few transitional millisecond pulsars that swing between an accretion-powered X-ray pulsar regime and a rotationally-powered radio pulsar regime in response to variations of the mass in-flow rate have been recently identified. Here we report the detection of optical pulsations from a transitional pulsar, the first ever from a millisecond spinning neutron star. The pulsations were observed when the pulsar was surrounded by an accretion disk and originated inside the magnetosphere or within a few hundreds of kilometres from it. Energy arguments rule out reprocessing of accretion-powered X-ray emission and argue against a process related to accretion onto the pulsar polar caps; synchrotron emission of electrons in a rotation-powered pulsar magnetosphere seems more likely.Comment: 32 pages, 7 figures. The first two authors contributed equally to this wor

GPU-based Real-time Triggering in the NA62 Experiment

Over the last few years the GPGPU (General-Purpose computing on Graphics Processing Units) paradigm represented a remarkable development in the world of computing. Computing for High-Energy Physics is no exception: several works have demonstrated the effectiveness of the integration of GPU-based systems in high level trigger of different experiments. On the other hand the use of GPUs in the low level trigger systems, characterized by stringent real-time constraints, such as tight time budget and high throughput, poses several challenges. In this paper we focus on the low level trigger in the CERN NA62 experiment, investigating the use of real-time computing on GPUs in this synchronous system. Our approach aimed at harvesting the GPU computing power to build in real-time refined physics-related trigger primitives for the RICH detector, as the the knowledge of Cerenkov rings parameters allows to build stringent conditions for data selection at trigger level. Latencies of all components of the trigger chain have been analyzed, pointing out that networking is the most critical one. To keep the latency of data transfer task under control, we devised NaNet, an FPGA-based PCIe Network Interface Card (NIC) with GPUDirect capabilities. For the processing task, we developed specific multiple ring trigger algorithms to leverage the parallel architecture of GPUs and increase the processing throughput to keep up with the high event rate. Results obtained during the first months of 2016 NA62 run are presented and discussed

Reconfigurable PCI Express cards for low-latency data transport in HEP experiments

State-of-the-art technology supports the High Energy Physics community in addressing the problem of managing an overwhelming amount of experimental data. From the point of view of communication between the detectors’ readout system and computing nodes, the critical issues are the following: latency, moving data in a deterministic and low amount of time; bandwidth, guaranteeing the maximum capability of the link and communication protocol adopted; endpoint consolidation, tight aggregation of channels on a single board. This contribution describes the status and performances of the NaNet project, whose goal is the design of a family of FPGA-based PCIe network interface cards. The efforts of the team are focused on implementing a low-latency, real-time data transport mechanism between the board network multi-channel system and CPU and GPU accelerators memories on the host. Several opportunities concerning technical solutions and scientific applications have been explored: NaNet-1 with a single GbE I/O interface, and NaNet-10, offering four 10GbE ports, for activities related to the GPU-based real-time trigger of NA62 experiment at CERN; NaNet3, with four 2.5Gbit optical channels, developed for the KM3NeT-ITALIA underwater neutrino telescope

Progress report on the online processing upgrade at the NA62 experiment

A new FPGA-based low-level trigger processor has been installed at the NA62 experiment. It is intended to extend the features of its predecessor due to a faster interconnection technology and additional logic resources available on the new platform. With the aim of improving trigger selectivity and exploring new architectures for complex trigger computation, a GPU system has been developed and a neural network on FPGA is in progress. They both process data streams from the ring imaging Cherenkov detector of the experiment to extract in real time high level features for the trigger logic. Description of the systems, latest developments and design flows are reported in this paper

Optical and ultraviolet pulsed emission from an accreting millisecond pulsar

Millisecond spinning, low-magnetic-field neutron stars are believed to attain their fast rotation in a 0.1–1-Gyr-long phase during which they accrete matter endowed with angular momentum from a low-mass companion star1. Despite extensive searches, coherent periodicities originating from accreting neutron star magnetospheres have been detected only at X-ray energies2 and in ~10% of the currently known systems3. Here we report the detection of optical and ultraviolet coherent pulsations at the X-ray period of the transient low-mass X-ray binary system SAX J1808.4−3658, during an accretion outburst that occurred in August 20194. At the time of the observations, the pulsar was surrounded by an accretion disk, displayed X-ray pulsations and its luminosity was consistent with magnetically funnelled accretion onto the neutron star. Current accretion models fail to account for the luminosity of both optical and ultraviolet pulsations; these are instead more likely to be driven by synchro-curvature radiation5,6 in the pulsar magnetosphere or just outside of it. This interpretation would imply that particle acceleration can take place even when mass accretion is going on, and opens up new perspectives in the study of coherent optical/ultraviolet pulsations from fast-spinning accreting neutron stars in low-mass X-ray binary systems

Performance of the NA62 trigger system

The NA62 experiment at CERN targets the measurement of the ultra-rare K+ ->pi+ nu nu decay, and carries out a broad physics programme that includes probes for symmetry violations and searches for exotic particles. Data were collected in 2016–2018 using a multi-level trigger system, which is described highlighting performance studies based on 2018 data

New measurement of the radiative decay Ke3g at the NA62 experiment at CERN

The NA62 experiment at CERN reports new results from the study of the radiative kaon decay K+→π0e+νγ (Ke3γ ), using a data sample recorded in 2017 and 2018. Preliminary results with the most precise measurement of the Ke3γ branching ratio, and a T-asymmetry measurement in the Ke3γ decay, are presented

Search for lepton number and flavour violation in K+ and pi0 decays

The NA62 experiment at CERN collected a large sample of charged kaon decays into final states with multiple charged particles in 2016-2018. This sample provides sensitivities to rare decays with branching ratios as low as 10 −11 . Searches for the lepton number violating K + → π − µ + e+ decay and the lepton flavour violating K + → π + µ − e + and π 0 → µ − e + decays are reported. No evidence for these decays is found and upper limits of the branching ratios are obtained at 90% confidence level. These results improve by one order of magnitude over previous results for these decay modes

Large Scale Low Power Computing System: Status of Network Design in ExaNeSt and EuroExa Projects

The deployment of the next generation computing platform at ExaFlops scale requires to solve new technological challenges mainly related to the impressive number (up to 106) of compute elements required. This impacts on system power consumption, in terms of feasibility and costs, and on system scalability and computing efficiency. In this perspective analysis, exploration and evaluation of technologies characterized by low power, high efficiency and high degree of customization is strongly needed. Among the various European initiative targeting the design of ExaFlops system, ExaNeSt and EuroExa are EU-H2020 funded initiatives leveraging on high end MPSoC FPGAs. Last generation MPSoC FPGAs can be seen as non-mainstream but powerful HPC Exascale enabling components thanks to the integration of embedded multi-core, ARM-based low power CPUs and a huge number of hardware resources usable to co-design application oriented accelerators and to develop a low latency high bandwidth network architecture. In this paper we introduce ExaNet the FPGA-based, scalable, direct network architecture of ExaNeSt system. ExaNet allow us to explore different interconnection topologies, to evaluate advanced routing functions for congestion control and fault tolerance and to design specific hardware components for acceleration of collective operations. After a brief introduction of the motivations and goals of ExaNeSt and EuroExa projects, we will report on the status of network architecture design and its hardware/software testbed adding preliminary bandwidth and latency achievements

Latest generation interconnect technologies in APEnet+ networking infrastructure

In this paper we present the status of the 3rd generation design of the APEnet board (V5) built upon the 28nm Altera Stratix V FPGA; it features a PCIe Gen3 x8 interface and enhanced embedded transceivers with a maximum capability of 12.5Gbps each. The network architecture is designed in accordance to the Remote DMA paradigm. The APEnet+ V5 prototype is built upon the Stratix V DevKit with the addition of a proprietary, third party IP core implementing multi-DMA engines. Support for zero-copy communication is assured by the possibility of DMA-accessing either host and GPU memory, offloading the CPU from the chore of data copying. The current implementation plateaus to a bandwidth for memory read of 4.8GB/s. Here we describe the hardware optimization to the memory write process which relies on the use of two independent DMA engines and an improved TLB